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Lattice Semiconductor
Figure 5-2. Block Diagram of Testbench Setup
Application Support
MAC FIFO Client
Interface
G/MII
Interface
test_ts_mac.v
ts_mac_top.v
Add Swap
and
Tx
pkt_mon
ethernet_pkts_sink
Loopback
TSMAC
Core
Rx
Rx_frame
Generator
Register
Interface
Orcastra
Interface
testcase.v
Orcastra
Driver
Note that the user can easily edit the testcase.v file to configure and monitor any registers they desire in the test
application design, as well modify the type or number of packets they wish to drive to the test application design.
Also note that the destination and source addresses can be swapped by enabling the swap control bit in the test
control register. Figure 5-3 shows a timing waveform of data and control signals on the ingress and egress sides of
the address swap module (when address swap is enabled).
Figure 5-3. Timing Waveform
rx_dbout
DST_ADD
SRC_ADD
Len/
Type
DST_ADD
FCS
rx_write
eof
rx_dbout
add_swap
SRC_ADD
DST_ADD
Len/
Type
DATA/PAD
FCS
rx_write_dly
eof_dly
IPUG51_03.0, December 2010
50
Tri-Speed Ethernet MAC User’s Guide
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